Click here to return to the VHDL Reference Guide. (last edit: 24. september 2012)

If

A sequential statement which executes one branch from a set of branches dependent upon the Conditions, which are tested in sequence.

Syntax

      [Label:] if Condition then
        SequentialStatements...
      [elsif Condition then
        SequentialStatements...]
      ... {any number of elsif parts}
      [else
        SequentialStatements...]
      end if [Label];
    

Where

See Sequential Statement

Things to remember

Be careful about the spelling of "elsif" and "end if"

Synthesis

Assignments within if statements generally synthesize to multiplexers. Incomplete assignments, where outputs remain unchanged for certain input conditions, synthesize to transparent latches in unclocked processes, and to recirculation in clocked processes. In some circumstances, nested if statements synthesize to multiple logic levels. This can be avoided by using a case statement instead.

Tips

A set of elsif branches can be used to give priority to the conditions tested first. To decode a value without giving priority to certain conditions, use a case statement instead.

Example

      if C1 = '1' and C2 = '1' then
        V := not V;
        W := '0';
        if C3 = '0' then
          X := A;
        elsif C4 = '0' then
          X := B;
        else
          X := C;
        end if;
      end if;
    

See Also

Case, Conditional Assignment, Generate